1. The Field of the Invention
The present invention relates the manufacture of semiconductor devices. More particularly, the present invention relates to a semiconductor wafer having semiconductor devices thereon, the semiconductor wafer having a substrate with a thin film thereon that is treated to prevent destructive stresses in the thin film, and a method of manufacture thereof.
2. The Relevant Technology
A layer of a material that is typically used in semiconductor device formation is a TiSi.sub.x, film which is layered upon a semiconductor wafer. TiSi.sub.x, films, when so used, are typically subjected to high temperature annealing cycles. During anneal process steps, grain growth of the films creates stresses that can damage or destroy the thin film. The stresses lead to warping and bowing and ultimately to film cracking which undermines desired low resistivity. The high temperature annealing cycles cause TiSi.sub.x films to experience low thermal stability. Additionally, problems are encountered with high overall sheet resistivity, and the variance thereof, of the TiSi.sub.x films. These problems all contribute to the problem of warping or bowing of semiconductor wafers associated with the use of TiSi.sub.x films used in the fabrication of semiconductor devices.
As seen in FIG. 1, a semiconductor wafer 10 has a substrate 12 with a layer of material 14 deposited thereover. After one or more heat treatments of semiconductor wafer 10, layer of material 14 incurs physical stress sufficient to induce a warpage in semiconductor wafer 10 as seen in FIG. 2. By way of example, layer of material 14 can be a metal silicide layer, such as a TiSi.sub.x film, which is composed of a plurality of grains 16 as is depicted in FIG. 3.
As it is known in the art that high-temperature annealing is required to achieve the minimum possible room-temperature resistivity of any given silicide, it is clear that advances are needed which will better control the mechanical and electrical stability of TiSi.sub.2 films during high temperature silicide formation and annealing.
Polycrystalline silicon (polysilicon) is the preferred material for gate electrodes in MOSFET structures. Polysilicon is advantageous over metal gate electrodes as it can withstand much higher subsequent processing temperatures before eutectic temperatures are reached. Polysilicon is readily deposited on bulk silicon or SiO.sub.2 using low pressure chemical vapor deposition (LPCVD).
As the drive toward integrating more active devices on a single integrated circuit necessitates the fabrication of increasingly small MOSFET structures, the resistance of the MOSFET gate becomes a limiting factor in device speed. As such, it is beneficial to use materials with the lowest possible sheet resistivities for making contact with the polysilicon gate structure. To this end, it is well known that refractory metal silicides can be readily formed on polysilicon MOSFET gate structures using conventional deposition techniques. The refractory metal silicides have low sheet resistivities after annealing and also form low resistance ohmic contacts with commonly used interconnect metals. The resistance of the silicide/polysilicon interface and its overall integrity are greatly affected by the manner in which the structures are processed.
Of all the available silicides, titanium silicide (TiSi.sub.2) has the lowest sheet resistivity when it has been annealed to its C54 crystalline phase. To obtain the desired low resistance requires high temperature annealing in the range of about 500.degree. to about 1100.degree. C. Numerous techniques for creating and annealing TiSi.sub.2 films on MOSFET source and drain electrodes are known, which techniques can be used in the present inventive method so as to obtain the desired low sheet resistivities. The most common of these techniques involve depositing, such as by sputtering, either pure titanium metal, or co-depositing stoichiometric titanium suicide (TiSi.sub.x), with subsequent annealing steps to convert the layer to TiSi.sub.2 in the C54 crystalline phase.
Typically, a thin film of titanium silicide is sputtered onto a substrate in preparation for making a semiconductor device. The sputtered layer is then annealed, for example in rapid thermal processing (RTP), at 1000.degree. C., for a period of about 20 seconds, and in an N.sub.2 environment. This anneal can be conducted as many as three times where the device is subjected to further RTP steps as the integrated circuit advances through the fabrication process to completion. Such high thermal cycles cause stress in a silicide-substrate interface due to dynamic grain morphology that results in warping and bowing of the structure. Warping and bowing lead to imperfect surfaces, which make it difficult to conduct photolithography and other processes. Such difficulties ultimately reduce yield in the fabrication process. More particular to the present invention, warping and bowing lead ultimately to cracks forming in the thin film and the resistivity of the film is increased because of discontinuous contact throughout the thin film.
Warping and bowing of titanium disilicide thin films is specifically caused by collapse of the grain structure that existed from the PVD sputtering and as a result, long grains form that set up the ultimately destructive stresses. Because poor thermal stability of thin films leads to a higher resistivity in a damaged film, the device is ultimately slower or it can even malfunction.
The use of TiSi.sub.2 in silicon gate MOSFET fabrication is becoming limited by insufficient process stability at the desired processing temperatures. This creates a problem as the trend toward increasingly complex integrated circuits necessitates an increasing number of high temperature processing steps after the deposition and formation of the silicide layer. Two specific unwanted side effects of the high temperature instability of TiSi.sub.2 are of interest in the present invention and are explained briefly below.
The first unwanted side effect results from stresses induced in the silicide film. Co-deposited TiSi.sub.x films contain numerous structural point defects, such as grain boundaries and dislocations. As the silicon wafer is subjected to temperatures in the range of about 500 to about 1,100.degree. C. in order to anneal the TiSi.sub.2, the grain structure of the TiSi.sub.2 changes from small to larger grains. If this stress becomes too large, cracks are induced in the TiSi.sub.2 films causing increased and uneven resistivity across the TiSi.sub.2 film. This results not only in slower MOSFET switching speeds but also in speeds which vary unacceptably from device to device on the same circuit die.
The second unwanted side effect also results from stresses induced in the TiSi.sub.2 film. Stresses caused by improperly controlled TiSi.sub.2 grain growth can result in warpage of the entire silicon wafer. In addition to the reliability concerns introduced by a warped wafer, warpage can contribute to lithographic alignment errors in subsequent patterning steps on fabrication lines that use projection patterning techniques. If a wafer surface becomes warped or wavy, the projected image will become distorted and cause improper image dimensions. This factor has becomes increasingly important as feature size decreases and wafer size increases. While wafer warpage can be limited by reducing the temperature ramp rates during high temperature long period annealing processes, this is usually not practical as semiconductor fabrication processes increasingly take advantage of the benefits of rapid thermal processing.
Accordingly, it would be an advance in the art to avoid the forgoing first and second unwanted side effect of stresses induced in a thin silicide film, and to reduce the mechanical semiconductor wafer stresses, develop superior sheet resistivity and thermal stability characteristics in TiSi.sub.2 films, and thus induce less warping and bowing on the semiconductor wafer due to annealing of the semiconductor wafer at high temperatures.